C3STREAM Land Designs delivers First IC chip:
~Ranjith, Saranya
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip.
One year back, we started learning the VLSI layout and design process with the support of “Aura Semiconductor Pvt Ltd” (Aura is a fabless semiconductor company innovating high-performance IC products for IoT Radios, Timing, and Portable Audio markets).
Over the year we have been involved with automation using SKILL (Lisp-based Cadence programming language) and layout workflow (python, shell scripting, etc), learning layout methodology, and aspects to keep in mind in layout. An example of SKILL code was the automation of a differential pair which is a very common circuit block in analog circuit design. This process in the last year has got us now only comfortable with the layout, but also the entire cadence flow and supported the group at Aura automate small aspects of their work.
We were trained in the layout by our mentor by assigning us small blocks that were used in real designs starting from digital and then analog. After completion of a layout, we got feedback from our mentor on matching, MOS transistors effects like LOD, constraints in floor planning and routing, accounting, or parasitic such as IR drops and capacitance. The time we took for each block also reduced as we worked on more blocks and we could see our progress in not only laying a block but also reduced time in making sure that it satisfied DRC (Design Rule Checker) and LVS (Layout vs schematic). This process of working on real blocks helped us improve our skill, speed, and confidence and gave us exposure to different kinds of blocks.
A couple of months back we were included in a team on an active project with Aura. We were able to complete around 40% of the layout from Auroville. It has opened opportunities for this high-tech work to be done out of Auroville. Currently, and Siva and Vasanthraj Gandhi (who are now part of the team) are being trained by us along with Aura in a similar fashion. Looking forward to layout and in time design many more IC designs.
Example of a top-level chip:
